I am a Senior Staff Engineer at Google, building AI supercomputers (TPUs). I work at the intersection of hardware, systems research, and performance engineering. Before Google, I received a Ph.D. from MIT (CSAIL), advised by Daniel Sanchez, where I helped develop new programming models and multi-core architectures for challenging forms of parallelism. My masters at MIT, advised by Li-Shiuan Peh, was on high-performance interconnection networks. Prior to MIT, I spent a wonderful four years as an undergraduate at IIT Madras.
AI Infrastructure (TPUs) | Google
I helped architect and land headline hardware features across multiple generations of TPUs that deliver O(2×) gen-over-gen performance improvements.
- SparseCore [1, 2] delivers O(2×) gen-over-gen performance for recommendation models that power Ads, Search, YouTube.
- Collective Acceleration Engine [3] delivers O(5×) latency improvement for collectives in low-latency LLM serving.
- Architect the TPU simulation ecosystem from cycle-level microarchitecture to analytical system-level models for LLM training, serving, and RL — directly informing multi-billion-dollar TPU and GPU investment decisions.
- Maintain an active research portfolio working with Ph.D. students and professors to explore and de-risk emerging paradigms at the intersection of AI and systems.
Parallel Computing | MIT
The Swarm architecture developed new programming models and multi-core architectures to tackle challenging forms of parallelism, and scale to hundreds of cores. It makes fine-grained parallelism practical by leveraging order as a general synchronization primitive. Swarm unlocks abundant parallelism scaling challenging applications from a broad set of domains including graph analytics, databases, machine learning, and discrete-event simulation. It outperforms state-of-the-art software-only parallel algorithms by one to two orders of magnitude, demonstrating speedups on applications that had eluded successful parallelization for decades.
Domain-specific Programmable Networks | MIT
PIFO introduced a simple, yet performant hardware abstraction (PIFO) for packet scheduling at line-rate in network routers. The Push-In First-Out Queue (PIFO) is a priority queue data structure that allows packets to be "pushed" (enqueued) into an arbitrary location in the queue, but only dequeued from the head. PIFOs enable programmable packet scheduling: by programming how each packet's location in the PIFO is computed as it arrives, PIFOs allow network operators to express a wide variety of practical schedulers. We demonstrated the feasibility of PIFOs in hardware (16-nm technology node) at high clock-rates typical in high-end switches of the day.
Interconnection Networks | MIT
The SCORPIO and SMART chips developed ideas that simplified cache coherence and multi-core programming, through novel on-chip network ordering primitives. SCORPIO was a 36-core processor taped out in a 45-nm process node: it was the first multi-core processor to demonstrate global ordering on a mesh network-on-chip (NoC), enabling a simple snoopy coherence protocol and memory consistency model, while achieving high multi-threaded performance. The SMART chip, taped out in a 45-nm technology node, demonstrated a novel low-swing clockless repeated link circuit that enabled multi-hop (virtual) single-cycle paths between cores, achieving low-power and low-latency network-on-chip (NoC) architectures.