I am a Senior Staff Engineer at Google, building AI supercomputers (TPUs). I work at the intersection of hardware, systems research, and performance engineering. Before Google, I received a Ph.D. from MIT (CSAIL), advised by Daniel Sanchez, where I helped develop new programming models and multi-core architectures for challenging forms of parallelism. My masters at MIT, advised by Li-Shiuan Peh, was on high-performance interconnection networks. Prior to MIT, I spent a wonderful four years as an undergraduate at IIT Madras.

AI Infrastructure (TPUs) | Google

I helped architect and land headline hardware features across multiple generations of TPUs that deliver O(2×) gen-over-gen performance improvements.

• SparseCore [1, 2] delivers O(2×) gen-over-gen performance for recommendation models that power Ads, Search, YouTube.
• Collective Acceleration Engine [3] delivers O(5×) latency improvement for collectives in low-latency LLM serving.
• Architect the TPU simulation ecosystem from cycle-level microarchitecture to analytical system-level models for LLM training, serving, and RL — directly informing multi-billion-dollar TPU and GPU investment decisions.
• Maintain an active research portfolio working with Ph.D. students and professors to explore and de-risk emerging paradigms at the intersection of AI and systems.

Parallel Computing | MIT

The Swarm architecture developed new programming models and multi-core architectures to tackle challenging forms of parallelism, and scale to hundreds of cores.

Domain-specific Programmable Networks | MIT

PIFO introduced a simple, yet performant hardware abstraction for packet scheduling at line-rate in network routers.

Interconnection Networks | MIT

The SCORPIO and SMART chips developed ideas that simplified cache coherence and multi-core programming, through novel on-chip network ordering primitives.